The invention relates to an integrated circuit comprising a substrate with analog and digital sub-circuits provided with different supply terminals, inter alia Vdd and Vss supply terminals for the analog part and a Vdd supply terminal for the digital part, and with a common substrate terminal or ground terminal, the supply terminals being connected to the substrate terminal or ground terminal via over-voltage protection circuits.
An integrated circuit of this type, comprising analog and digital circuit parts, is known from European patent application 0.688.079.
Substrate currents caused by switching transistors form a source of noise within integrated circuits with mixed analog and digital signals. This substrate noise may disturb sensitive analog circuits, such as receiver circuits for mobile radio communication. In order to preclude this, the analog circuits in question should be designed so as to be insensitive to substrate noise.
In integrated circuits of, for example, the CMOS type (xe2x80x9cComplementary-Metal-Oxide-Semiconductorxe2x80x9d) comprising a low-impedance substrate, the substrate currents can enter the circuits from the bottom of the substrate.
To preclude this, the analog circuits should be formed in the substrate so as to be isolated from said substrate. This isolation is effective only if MOS-technology is used without source/substrate connections. Only then the analog circuit part has a xe2x80x9ccleanxe2x80x9d analog ground, which is not connected to the substrate.
Persons skilled in the art know that integrated circuits also have to be protected against damage caused by electrostatic discharge (xe2x80x9cElectro Static Dischargexe2x80x9d) (ESD), which is characterized by pulses of a high voltage (a few kV), a short duration (a few ns) and an average current intensity (a few A). The human body, electric fields generated by machines, and such, are sources of ESD which are well-known in practice.
In the case of mixed (digital and analog) integrated circuits, the analog part of which is isolated from the substrate, the problem arises that the path for ESD currents is not defined when the Vss supply terminal of the analog part is not connected to the substrate. In particular over-voltages on the supply terminals of the analog circuits may then lead to interference and damage.
In practice, generally two techniques are employed to solve this problem. On the one hand, a xe2x80x9cbondingxe2x80x9d technique is employed, whereby the relevant Vss supply terminal is electroconductively connected to the substrate, or, on the other hand, a technique whereby anti-parallel-connected diodes are incorporated between the analog Vss supply terminal and the substrate. However, both measures lead to an undesirable increase of the substrate noise coupling via the Vss supply terminal.
In general, it applies that there is a correlation between optimum ESD protection and minimum noise coupling. A direct, electroconductive connection between the Vss supply terminal of the analog sub-circuits and the substrate is optimal from the point of view of ESD. Complete electrical insulation, on the other hand, is optimal for achieving a minimum substrate noise coupling.
Studies into ESD phenomena have shown that over-voltages between the Vdd supply terminal of the analog part (hereinafter referred to as analog Vdd supply terminal, for short) and the analog Vss supply terminal are the principal cause of internal errors in the analog part. Reference is made, inter alia, to Wei et.al., xe2x80x9cEffect of Substrate Contact on ESD Failure of Advanced CMOS Integrated Circuitsxe2x80x9d, EOS/ESD Symposium 1993, pp. 221-224.
These errors can be attributed to, inter alia, a xe2x80x9clatch upxe2x80x9d or xe2x80x9csnap backxe2x80x9d caused by ESD, as a result of which, in MOS transistors with a floating gate or a grounded gate, an over-voltage on an n+ or p+ diffusion region causes a bipolar effect to be maintained in the reverse direction beyond the avalanche breakdown voltage and it causes a relatively high current flow. Particularly, small diffusion regions connected to the analog Vss supply terminal run the risk of damage by the xe2x80x9clatch upxe2x80x9d or xe2x80x9csnap backxe2x80x9d effect.
Partly because of their xe2x80x9csnap backxe2x80x9d properties, MOS transistors are generally used in practice as over-voltage protection circuit or as a protection against ESD. This can be attributed to the fact that customary bipolar diodes do not protect sufficiently against ESD phenomena owing to their higher differential resistance and higher power dissipation during avalanche breakdown in the reverse direction, so that, according to the currently prevailing design principles for ESD protection, persons skilled in the art generally do not use said bipolar diodes. MOS transistors with a grounded gate, on the other hand, do exhibit a sufficiently low differential resistance in the reverse direction to neutralize ESD over-voltages, which can be partly attributed to the xe2x80x9clatch upxe2x80x9d or xe2x80x9csnap backxe2x80x9d effect.
It is an object of the invention to provide both an improved ESD protection and a reduced substrate noise coupling in an integrated circuit of the mixed type, i.e. comprising mutually isolated digital and analog circuit parts.
In accordance with the invention, this object is achieved in that, an element having a diode function is formed in the substrate between the Vdd and Vss supply terminals of an analog sub-circuit, which element comprises a cathode part which is connected to the Vdd supply terminal and an anode part which is connected to the Vss supply terminal of the relevant analog sub-circuit, and the over-voltage protection circuits for the analog sub-circuit are embodied so as to act only in the case of positive over-voltages on a supply terminal with respect to the substrate.
The relevant over-voltage protection circuits in combination with the diode element arranged in the above-mentioned manner provide, in contravention to the customary design rules, an effective protection against ESD, which comes as a surprise to experts in the field of ESD over-voltage protection in power supplies.
The fact is that the diode element, which is arranged in the reverse direction between the analog Vdd and Vss supply terminals, forms a well-defined over-voltage path for negative over-voltages on the analog Vdd supply terminal with respect to the analog Vss supply terminal. In the case of a negative over-voltage on the analog Vdd supply terminal, the ESD current caused thereby will flow through the relevant diode element, not through the analog circuit part. Positive over-voltages on the analog supply terminals are handled by the relevant over-voltage protection circuits.
It can be additionally realized that the single diode element in accordance with the invention, in combination with the xe2x80x9cpositivexe2x80x9d over-voltage protections between the supply terminals and the substrate, provides an improved substrate noise coupling, as opposed to, for example, anti-parallel arranged diodes, for which it holds that throughout the relevant noise-voltage area between the substrate and the analog Vss supply terminal, a relatively large diffusion capacitance, in the forward direction, of each time one of the relevant diodes is available.
Consequently, the invention combines a reduced substrate noise coupling with an improved ESD behavior. To persons skilled in the art it will be clear that this is a great advantage for integrated circuits comprising both digital and analog sub-circuits.
The over-voltage protection circuits, which are connected to the supply terminals and the substrate terminal or ground terminal, may be of the thick field-oxide type or may comprise a MOS transistor which is connected with its drain to the substrate terminal or ground terminal, such as a N-channel MOS transistor.
In a further embodiment, the element with diode action is provided by one or more adjacent p-n junctions formed in the substrate, which p-n junctions may be, respectively, p+ and n+ diffusion regions.
The invention will be explained in greater detail hereinbelow with reference to the Figures representing circuit diagrams.